The SPLV2.8-4 was designed to protect low voltage,CMOS devices from ESD and lightning induced transients.
There is a compensating diode in series with each lowvoltage TVS to present a low loading capacitance to theline being protected. These robust structures can safelyabsorb repetitive ESD strikes at ±30kV (contact discharge)per IEC61000-4-2 standard and each structure can safelydissipate up to 40A (IEC61000-4-5, tP=8/20μs) with verylow clamping voltages.
ESD, IEC61000-4-2, ±30kV contact, ±30kV air
EFT, IEC61000-4-4, 40A (5/50ns)
Lightning, IEC61000-4-5, 40A (8/20μs)
Low capacitance of 2pF per line
Low leakage current of 1μA (MAX) at 2.8V
SOIC-8 (JEDEC MS-012) pin configuration allows for simple flow-through layout